Sr. Verification Engineer (ASIC)

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Job Title: Sr. Verification Engineer (ASIC) Position Type: Contracted - 10/12/2026 - 06/30/2026 Job Type: 100% Remote (If converted, you will have to relocate to one of the client location, Southern California or Austin, TX) Pay rate: $100/-hr to $110/-hr on W2 Job Description: As a Senior Verification Engineer on the ASIC Networking team, you support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with first tapeout targeted for 2027. Verification strategy, methodology, and infrastructure are being defined now, and you help define them. The work spans IP, subsystem, and full SoC verification, including CPU subsystems, performance-critical interconnects, security, high-speed peripherals, modem datapath and PHY layers, DSP and beamforming compute, and mixed-signal interfaces. You own a subset of this scope aligned to your background. The team treats constrained-random simulation, formal methods, and processor-driven SoC testing as equal first-class tools, and is building an AI-enabled verification platform that includes LLM-assisted stimulus and testbench generation, automated regression triage and failure clustering, and data-driven coverage closure. Because none of this is inherited, the engineers who build these capabilities will own them - and grow with the program as it scales. Background in wireless communications, modem, baseband, and DSP verification is welcome but not required. Architects and modeling engineers support your ramp, and verification judgment and system-level thinking are weighted above domain background. Responsibilities: Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off. Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios. Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing. Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions. Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results. Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels. Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics. Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology. Basic Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience. Minimum five years of professional experience in ASIC or SoC functional verification. Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance. Experience with metric-driven verification for planning, assertions, and functional coverage closure. Experience verifying complex digital control and datapath logic, including RTL and system-level debug. Preferred Qualifications: Background in space-based communications, wireless communications, or modem, baseband, or DSP hardware. Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis. Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties. Experience with interconnect or NoC verification covering performance, bandwidth, QoS, and deadlock analysis. Experience verifying fault tolerance and reliability features such as ECC, redundancy schemes, or fault injection. Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios. Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis. wing alongside the FSBR team and day-to-day m

职位名称：高级验证工程师（ASIC）
职位类型：合同制 - 2026/10/12 - 2026/06/30
工作类型：100%远程（如果转正，您需要搬迁到客户所在地之一，南加州或德克萨斯州奥斯汀）
薪资：W2每小时100美元至110美元

职位描述：
作为ASIC网络团队的高级验证工程师，您将支持TeraWave首个内部硅片项目，该项目包括一个高吞吐量调制解调器和一个DSP密集型数字波束成形器，首次流片目标为2027年。验证策略、方法和基础设施目前正在定义中，您将帮助定义它们。工作范围涵盖IP、子系统和完整SoC验证，包括CPU子系统、性能关键互连、安全、高速外设、调制解调器数据通路和PHY层、DSP和波束成形计算以及混合信号接口。您将根据自身背景负责其中一部分范围。团队将约束随机仿真、形式化方法和处理器驱动的SoC测试视为同等的一流工具，并正在构建一个AI赋能的验证平台，包括LLM辅助的激励和测试平台生成、自动化回归分类和故障聚类以及数据驱动的覆盖率收敛。由于这些都不是继承而来的，构建这些能力的工程师将拥有它们——并随着项目扩展而成长。欢迎具有无线通信、调制解调器、基带和DSP验证背景，但并非必需。架构师和建模工程师将支持您的上手，验证判断力和系统级思维比领域背景更重要。

职责：
- 负责复杂模块和子系统的验证规划和执行，从测试计划到签核。
- 将设计规格转化为验证策略、可衡量的覆盖率目标和高风险场景的早期识别。
- 为每个问题选择验证方法，包括约束随机仿真、形式化分析和定向测试。
- 开发验证环境、参考模型、记分板、协议监视器、覆盖率组件和断言。
- 推动功能覆盖率收敛、回归健康和跨仿真及形式化结果的签核准备。
- 构建验证基础设施、回归和CI系统，以及跨IP、子系统和SoC级别的复用策略。
- 应用并构建AI辅助验证能力，用于激励生成、回归分类和覆盖率分析。
- 审查测试平台架构和调试方法，并在验证方法方面指导初级工程师。

基本资格：
- 电气工程、计算机工程或相关领域学士学位，或7年以上同等经验。
- 至少五年ASIC或SoC功能验证的专业经验。
- 在SystemVerilog、UVM或形式化测试平台开发和维护方面具有实践经验。
- 具有指标驱动验证的经验，包括规划、断言和功能覆盖率收敛。
- 具有验证复杂数字控制和数据通路逻辑的经验，包括RTL和系统级调试。

优先资格：
- 具有天基通信、无线通信或调制解调器、基带或DSP硬件背景。
- 具有使用位精确参考模型和定点分析验证LDPC、FEC、成帧或波束成形逻辑的经验。
- 在生产硅片上具有形式化验证经验，包括连接性、寄存器映射、仲裁、CDC或安全属性。
- 具有互连或NoC验证经验，涵盖性能、带宽、QoS和死锁分析。
- 具有验证容错和可靠性特性的经验，如ECC、冗余方案或故障注入。
- 具有为SoC、CPU启动和固件驱动测试场景开发基于C或可移植激励的经验。
- 具有将AI、ML或LLM工具应用于激励生成、回归分类或覆盖率分析的经验。
与FSBR团队并肩工作，以及日常m

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