Staff Physical Design Engineer

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EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is looking for a highly motivated and experienced Staff Physical Design Engineer to drive the physical implementation of our next-generation semiconductor chips. In this role, you will play a critical part in translating complex microarchitectures into high-performance, power-efficient silicon. Working closely with cross-functional teams, you will own block-level and top-level implementation using industry-standard EDA tools, tackle complex timing closure and power challenges, and guide designs all the way from netlist to successful foundry tapeout. Key Responsibilities Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing. Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques. Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution. Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies. Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution. Qualifications and Requirements Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 10–15 years of dedicated experience in physical design. Strong understanding of EDA implementation flows with extensive experience using Cadence design tools. Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies. Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus. Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification. Strong scripting skills in Tcl or Python for design flow automation. Solid understanding of advanced process nodes and physical verification requirements associated with routing. Experience with physical design methodology, flow setup, and advanced flow evaluations. Prior experience with PDK management or foundry tapeout processes is highly desirable. EnCharge AI is an equal employment opportunity employer in the United States. The salary range for this position is $170,000 to $240,000 USD ($170,000 to $230,000 CAD) per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience. Originally posted on Himalayas

EnCharge AI是面向边缘到云计算的高级AI硬件与软件系统领域的领导者。EnCharge强大且可扩展的下一代存内计算技术，与当今一流的解决方案相比，可提供高出数个数量级的计算效率和密度。高性能架构与无缝软件集成相结合，将使AI的巨大潜力在功率、能源和空间受限的应用中得以实现。EnCharge AI成立于2022年，由在半导体设计和AI系统领域拥有深厚背景的资深技术专家领导。 关于该职位 EnCharge AI正在寻找一位积极主动、经验丰富的资深物理设计工程师，推动我们下一代半导体芯片的物理实现。在该职位中，您将在把复杂微架构转化为高性能、低功耗硅片的过程中发挥关键作用。您将与跨职能团队紧密合作，使用行业标准EDA工具负责模块级和顶层实现，攻克复杂的时序收敛和功耗挑战，并引导设计从网表一直到成功流片。 主要职责 推动模块级和顶层物理设计，包括布局规划、布局、时钟树综合（CTS）和布线。 通过先进的时序收敛技术实现严苛的时序、功耗和面积（PPA）目标。 执行电源网格验证，并管理电迁移和IR压降（EM/IR）分析与解决。 开发并维护自动化脚本（Tcl/Python），以简化设计流程和方法学。 与物理验证和代工厂团队合作，确保设计规则合规并成功执行流片。 资格与要求 电气工程、计算机工程或相关领域的学士或硕士学位。 10–15年专注于物理设计的经验。 对EDA实现流程有深入理解，并具有丰富的Cadence设计工具使用经验。 深入理解静态时序分析（STA）概念和先进的时序收敛方法学。 在顶层和模块级物理设计方面有可证明的成功经验，具备层次化布局规划专长者优先。 精通低功耗设计技术、调试以及EM/IR检查解决/电源网格验证。 具备较强的Tcl或Python脚本能力，用于设计流程自动化。 对先进工艺节点及与布线相关的物理验证要求有扎实理解。 具有物理设计方法学、流程搭建和先进流程评估的经验。 具有PDK管理或代工厂流片流程经验者优先。 EnCharge AI是美国平等就业机会雇主。该职位的薪资范围为每年170,000至240,000美元（170,000至230,000加元）。实际提供的薪酬将根据与工作相关的知识、技能和经验确定。 原发布于Himalayas

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